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74LVC4245A
Octal dual supply translating transceiver; 3-state
Rev. 06 -- 18 January 2008 Product data sheet
1. General description
The 74LVC4245A is an octal dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment. The device features an output enable input (pin OE) for easy cascading and a send/receive input (pin DIR) for direction control. Pin OE controls the outputs so that the buses are effectively isolated. In suspend mode, when VCCA is zero, there will be no current flow from one supply to the other supply. The A-outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCCA VCCB, except in suspend mode.
2. Features
I 5 V tolerant inputs/outputs, for interfacing with 5 V logic I Wide supply voltage range: N 3 V port (VCCB): 1.5 V to 3.6 V N 5 V port (VCCA): 1.5 V to 5.5 V I CMOS low-power consumption I Direct interface with TTL levels I Inputs accept voltages up to 5.5 V I High-impedance when VCC = 0 V I Complies with JEDEC standard no. JESD8B/JESD36 I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Multiple package options I Specified from -40 C to +85 C and -40 C to +125 C
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
3. Ordering information
Table 1. Ordering information Package Temperature range 74LVC4245AD 74LVC4245ADB 74LVC4245APW 74LVC4245ABQ -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C Name SO24 SSOP24 TSSOP24 DHVQFN24 Description plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm Version SOT137-1 SOT340-1 Type number
plastic thin shrink small outline package; 24 leads; SOT355-1 body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm SOT815-1
4. Functional diagram
2
DIR OE
22
3
A0 B0 21
4 22 2 G3 3EN1 3EN2 5
A1 B1 A2 B2 19 20
1 3 4 5 6 7 8 9 10
mna452
6 2 21 20 19 8 18 17 16 15 14 10 9 7
A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 14 15 16 17 18
mna453
Fig 1.
IEC Logic symbol
Fig 2.
Logic diagram
74LVC4245A_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
2 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
5. Pinning information
5.1 Pinning
74LVC4245A
VCCA terminal 1 index area 24 VCCB 23 VCCB 22 OE 21 B0 20 B1 19 B2 18 B3 17 B4 16 B5 GND(1) GND 12 GND 13 15 B6 14 B7
74LVC4245A
DIR VCCA DIR A0 A1 A2 A3 A4 A5 A6 1 2 3 4 5 6 7 8 9 24 VCCB 23 VCCB 22 OE 21 B0 20 B1 19 B2 18 B3 17 B4 16 B5 15 B6 14 B7 13 GND
001aaa349
2 3 4 5 6 7 8 9
A0 A1 A2 A3 A4 A5 A6
A7 10 GND 11
A7 10 GND 11 GND 12
1
001aah087
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 3.
Pin configuration SO24 and (T)SSOP24
Fig 4.
Pin configuration DHVQFN24
5.2 Pin description
Table 2. Symbol VCCA VCCB GND DIR A[0:7] B[0:7] OE Pin description Pin 1 23, 24 11, 12, 13 2 3, 4, 5, 6, 7, 8, 9, 10 21, 20, 19, 18, 17, 16, 15, 14 22 Description supply voltage (5 V bus) supply voltage (3 V bus) ground (0 V) direction control data input or output data input or output output enable input (active LOW)
74LVC4245A_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
3 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
6. Functional description
Table 3. Input OE L L H
[1]
Functional table[1] Input/output DIR L H X An A=B input Z Bn input B=A Z
H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state.
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCCA VCCB IIK VI IOK VO IO ICC IGND Tstg Ptot
[1] [2]
Parameter supply voltage 5 V port supply voltage 3 V port input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature power dissipation
Conditions
Min -0.5 -0.5
Max +6.5 +4.6 +6.5 50 VCC + 0.5 +6.5 50 100 +150 500
Unit V V mA V mA V V mA mA mA C mW
VI < 0 V
[1]
-50 -0.5 [1] [1]
VO > VCC or VO < 0 V output HIGH or LOW state output 3-state VO = 0 V to VCC
-0.5 -0.5 -100 -65
Tamb = -40 C to +125 C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO24 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For (T)SSOP24 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN24 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5. Symbol VCCA VCCB VI VO Tamb
74LVC4245A_6
Recommended operating conditions Parameter supply voltage 5 V port (for maximum speed performance) Conditions VCCA VCCB; see Figure 5 Min 1.5 1.5 0 0 0 -40 Typ Max 5.5 3.6 5.5 VCC 5.5 +125 Unit V V V V V C
supply voltage 3 V port (for low-voltage VCCA VCCB; see Figure 5 applications) input voltage output voltage ambient temperature for control inputs output HIGH or LOW state output 3-state
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
4 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
Table 5. Symbol t/V
Recommended operating conditions ...continued Parameter input transition rise and fall rate Conditions VCCB = 2.7 V to 3.0 V VCCB = 3.0 V to 3.6 V VCCA = 3.0 V to 4.5 V VCCA = 4.5 V to 5.5 V Min Typ Max 20 10 20 10 Unit ns/V ns/V ns/V ns/V
9. Static characteristics
Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIH VIL VOH Parameter HIGH-level input voltage LOW-level input voltage Conditions VCCB = 2.7 V to 3.6 V VCCA = 4.5 V to 5.5 V VCCB = 2.7 V to 3.6 V VCCA = 4.5 V to 5.5 V HIGH-level output voltage VI = VIH or VIL VCCB = 2.7 V to 3.6 V; IO = -100 A VCCB = 2.7 V; IO = -12 mA VCCB = 3.0 V; IO = -24 mA VCCA = 4.5 V to 5.5 V; IO = -100 A VCCA = 4.5 V; IO = -12 mA VCCA = 4.5 V; IO = -24 mA VOL LOW-level output voltage VI = VIH or VIL VCCB = 2.7 V to 3.6 V; IO = 100 A VCCB = 2.7 V; IO = 12 mA VCCB = 3.0 V; IO = 24 mA VCCA = 4.5 V to 5.5 V; IO = 100 A VCCA = 4.5 V; IO = 12 mA VCCA = 4.5 V; IO = 24 mA II IOZ input leakage current OFF-state output current VI = 5.5 V or GND VI = VIH or VIL VCCB = 3.6 V; VO = VCCB or GND VCCA = 5.5 V; VO = VCCA or GND ICC supply current IO = 0 A VCCB = 3.6 V; other inputs at VCCB or GND VCCA = 5.5 V; other inputs at VCCA or GND 0.1 0.1 10 10 A A
[2]
Min 2.0 2.0 VCCB - 0.2 VCCB - 0.5 VCCB - 0.8 VCCA - 0.2 VCCA - 0.5 VCCA - 0.8 -
Typ[1] VCCB VCCA 0.1 0.1 0.1
Max 0.8 0.8 0.20 0.40 0.55 0.20 0.40 0.55 5 5 5
Unit V V V V V V V V V V V V V V V V A A A
Tamb = -40 C to +85 C
74LVC4245A_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
5 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
Table 6. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol ICC Parameter additional supply current Conditions per control pin; IO = 0 A VCCB = 2.7 V to 3.6 V; VI = VCCB - 0.6 V; other inputs at VCCB or GND VCCA = 4.5 V to 5.5 V; VI = VCCA - 0.6 V; other inputs at VCCA or GND CI CI/O VIH VIL VOH input capacitance input/output capacitance HIGH-level input voltage LOW-level input voltage An and Bn VCCB = 2.7 V to 3.6 V VCCA = 4.5 V to 5.5 V VCCB = 2.7 V to 3.6 V VCCA = 4.5 V to 5.5 V HIGH-level output voltage VI = VIH or VIL VCCB = 2.7 V to 3.6 V; IO = -100 A VCCB = 2.7 V; IO = -12 mA VCCB = 3.0 V; IO = -24 mA VCCA = 4.5 V to 5.5 V; IO = -100 A VCCA = 4.5 V; IO = -12 mA VCCA = 4.5 V; IO = -24 mA VOL LOW-level output voltage VI = VIH or VIL VCCB = 2.7 V to 3.6 V; IO = 100 A VCCB = 2.7 V; IO = 12 mA VCCB = 3.0 V; IO = 24 mA VCCA = 4.5 V to 5.5 V; IO = 100 A VCCA = 4.5 V; IO = 12 mA VCCA = 4.5 V; IO = 24 mA II IOZ input leakage current OFF-state output current VI = 5.5 V or GND VI = VIH or VIL VCCB = 3.6 V; VO = VCCB or GND VCCA = 5.5 V; VO = VCCA or GND ICC supply current IO = 0 A VCCB = 3.6 V; other inputs at VCCB or GND VCCA = 5.5 V; other inputs at VCCA or GND 40 40 A A
[2] [3]
Min -
Typ[1] 5
Max 500
Unit A
-
5
500
A
2.0 2.0 VCCB - 0.3 VCCB - 1.0 VCCA - 0.3 VCCA - 1.0 -
4.0 5.0 -
0.8 0.8 0.30 0.60 0.80 0.30 0.60 0.80 20 20 20
pF pF V V V V V V V V V V V V V V V V A A A
Tamb = -40 C to +125 C
VCCB - 0.65 -
VCCA - 0.65 -
74LVC4245A_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
6 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
Table 6. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol ICC Parameter additional supply current Conditions per control pin; IO = 0 A VCCB = 2.7 V to 3.6 V; VI = VCCB - 0.6 V; other inputs at VCCB or GND VCCA = 4.5 V to 5.5 V; VI = VCCA - 0.6 V; other inputs at VCCA or GND
[1] [2] [3] All typical values are measured at VCCA = 5.0 V, VCCB = 3.3 V and Tamb = 25 C. For transceivers, the parameter IOZ includes the input leakage current. VCCB = 2.7 V to 3.6 V: other inputs at VCCB or GND. VCCA = 4.5 V to 5.5 V: other inputs at VCCA or GND.
[3]
Min -
Typ[1] -
Max 5000
Unit A
-
-
5000
A
10. Dynamic characteristics
Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). VCCA = 4.5 V to 5.5 V; tr = tf 2.5 ns. For test circuit see Figure 8. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions An to Bn; see Figure 6 Bn to An; see Figure 6 An to Bn; see Figure 6 Bn to An; see Figure 6 OE to An; see Figure 7 OE to Bn; see Figure 7 OE to An; see Figure 7 OE to Bn; see Figure 7 OE to An; see Figure 7 OE to Bn; see Figure 7 OE to An; see Figure 7 OE to Bn; see Figure 7 VCCB 2.7 V 3.0 V to 3.6 V 2.7 V 3.0 V to 3.6 V 2.7 V 3.0 V to 3.6 V 2.7 V 3.0 V to 3.6 V 2.7 V 3.0 V to 3.6 V 2.7 V 3.0 V to 3.6 V 2.7 V 3.0 V to 3.6 V 2.7 V 3.0 V to 3.6 V 2.7 V 3.0 V to 3.6 V 2.7 V 3.0 V to 3.6 V 2.7 V 3.0 V to 3.6 V 2.7 V 3.0 V to 3.6 V 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 -40 C to +85 C Min Typ[1] 3.6 3.3 3.4 3.4 3.3 2.8 3.0 3.0 4.5 4.5 4.4 3.8 4.5 4.5 4.3 3.2 2.9 2.9 3.9 3.5 2.8 2.8 3.3 2.9 Max 6.3 6.3 6.1 6.1 6.7 6.5 5.0 5.0 9.0 9.0 8.7 8.1 8.1 8.1 8.7 8.1 7.0 7.0 7.7 7.7 5.8 5.8 7.8 7.8 -40 C to +125 C Unit Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 8.0 8.0 8.0 8.0 8.5 8.5 6.5 6.5 11.5 11.5 11.0 10.5 10.5 10.5 11.0 10.5 9.0 9.0 10.0 10.0 7.5 7.5 10.0 10.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
7 of 17
tPLH
LOW to HIGH propagation delay
tPZL
OFF-state to LOW propagation delay OFF-state to HIGH propagation delay LOW to OFF-state propagation delay HIGH to OFF-state propagation delay
tPZH
tPLZ
tPHZ
74LVC4245A_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
Table 7. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V). VCCA = 4.5 V to 5.5 V; tr = tf 2.5 ns. For test circuit see Figure 8. Symbol Parameter tsk(o) CPD output skew time power dissipation capacitance 5 V port: Bn to An; VI = GND to VCCA; VCCA = 5.0 V outputs enabled outputs disabled 3 V port: An to Bn; VI = GND to VCCB; VCCB = 3.3 V outputs enabled outputs disabled
[1] [2] [3]
Conditions
VCCB
[2]
-40 C to +85 C Min Typ[1] Max 1.0
-40 C to +125 C Unit Min Max 1.5 ns
[3]
[3]
-
17 5
-
-
-
pF pF
-
-
17 5
-
-
-
pF pF
Typical values are measured at Tamb = 25 C, VCCA = 5.0 V, and VCCB = 2.7 V and 3.3 V respectively. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL x VCC2 x fo) = sum of the outputs
11. AC waveforms
mna454
3.9 VCCB (V) 3.6 3.3 3.0 2.7 2.4 2.1 1.8 1.5 1.2 0.9
VCCA VCCB
1.5
2.1
2.7
3.3
3.9
4.5
5.1 5.7 VCCA (V)
Full operation
Complies with TTL levels
Fig 5.
Supply operation area
74LVC4245A_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
8 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
VI An, Bn input GND t PHL VOH Bn, An output VOL VM
mna366
VM
t PLH
VM = 1.5 V at 2.7 V VCCB 3.6 V; VM = 0.5VCCA at VCCA 4.5 V. VOL and VOH are typical output voltage drops that occur with the output load.
Fig 6.
Input (An, Bn) to output (Bn, An) propagation delays
VI OE input GND t PLZ VCC output LOW-to-OFF OFF-to-LOW VOL t PHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled
mna367
VM
t PZL
VM VX t PZH VY VM
VM = 1.5 V at 2.7 V VCCB 3.6 V; VM = 0.5VCCA at VCCA 4.5 V. VX = VOL + 0.3 V at VCCB 2.7 V; VY = VOH - 0.3 V at VCCB 2.7 V. VOL and VOH are typical output voltage drops that occur with the output load.
Fig 7.
3-state enable and disable times
74LVC4245A_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
9 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
VEXT VCC VI VO DUT
RT CL RL RL
G
mna616
Test data is given in Table 8. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 8. Table 8. VCCA < 2.7 V -
Load circuitry for switching times Test data Input VCCB < 2.7 V 2.7 V to 3.6 V VI [1] VCCI 2.7 V 3.0 V Load CL 50 pF 50 pF 50 pF RL 500 500 500 VEXT tPLH, tPHL open open open tPZH, tPHZ GND GND GND tPZL, tPLZ [2] 2 x VCCO 2 x VCCO 2 x VCCO
Supply voltage
4.5 V to 5.5 V
[1] [2]
VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port.
74LVC4245A_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
10 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 9.
74LVC4245A_6
Package outline SOT137-1 (SO24)
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
11 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 12 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 8 o 0
o
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT340-1 (SSOP24)
74LVC4245A_6 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
12 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c y HE vMA
Z
24
13
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
12
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8o 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 11. Package outline SOT355-1 (TSSOP24)
74LVC4245A_6 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
13 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
SOT815-1
D
B
A
E
A
A1 c
detail X terminal 1 index area C terminal 1 index area 2 L 12 e1 e b 11 vMCAB wM C y1 C y
1
Eh
e2
24 13
23 Dh 0
14 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.6 5.4 Dh 4.25 3.95 E (1) 3.6 3.4 Eh 2.25 1.95 e 0.5 e1 4.5 e2 1.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT815-1 REFERENCES IEC --JEDEC --JEITA --EUROPEAN PROJECTION
ISSUE DATE 03-04-29
Fig 12. Package outline SOT815-1 (DHVQFN24)
74LVC4245A_6 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
14 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
13. Abbreviations
Table 9. Acronym ESD HBM MM TTL Abbreviations Description ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic
14. Revision history
Table 10. Revision history Release date 20080118 Data sheet status Product data sheet Change notice Supersedes 74LVC4245A_5 Document ID 74LVC4245A_6 Modifications:
* * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN24 package added. Section 7: derating values added for DHVQFN24 package. Section 12: outline drawing added for DHVQFN24 package. Product specification Product specification Product specification Product specification Product specification 74LVC4245A_4 74LVC4245A_3 74LVC4245A_2 74LVC4245A_1 -
74LVC4245A_5 74LVC4245A_4 74LVC4245A_3 74LVC4245A_2 74LVC4245A_1
20040330 20040211 19990615 19980729 19980729
74LVC4245A_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
15 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC4245A_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 18 January 2008
16 of 17
NXP Semiconductors
74LVC4245A
Octal dual supply translating transceiver; 3-state
17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 January 2008 Document identifier: 74LVC4245A_6

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